A method and circuit structure for determining the value of discrete components on mixed-signal boards was proposed in pending application U.S. patent application Ser. No. 08/071,461 filed Jun. 2, 1993, now abandoned and assigned to the assignee of the present invention. The structure defines cells to be placed at analog pins of an integrated circuit (IC), with each cell made up of five switches. Two analog buses are used to interconnect voltage supply, ground, analog core circuit in the IC, and the discrete components on board, in different configurations by controlling the switches in the cells. A current source is used as stimulus through one analog bus and a voltmeter measures voltage using another analog bus. The given metrology provides for measurement of voltages at the pins of an IC connected to a discrete component network (DCN), by passing a fixed current through the pins. The DCN can then be verified using the measured voltages. The switches in the cells are controlled by instructions using the JTAG/IEEE 1149.1 TAP controller, see "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE Standard 1149.1-1990. A minimum of six extra pins (four for JTAG and two for the analog buses) are required on each mixed-signal IC in this approach.
The circuit structure described in the aforementioned patent application is shown schematically in FIGS. 1-3. In FIG. 1 an integrated circuit U1, contains four analog test pins 10-16 connected with an analog core circuit 18 through respective test cells 20-26. Analog buses 28 and 30 are connected with each test cell and to bus pins 32 and 34 of the circuit U1. As shown in greater detail in FIG. 2, each test cell includes five switches labeled V, G, S.sub.1, S.sub.2 and CD. These switches control the connection of the test pin to power rail (V.sub.dd), ground, analog buses 28 and 30, and the analog core circuit 18, respectively. The core disconnect switch (CD) is conceptual and can be designed as part of the core circuit to minimize adverse effects on performance. FIG. 3 shows three mixed-signal ICs, generally designated U1, U2, and U3, interconnected with three different DCNs. The ICs and DCNs are all mounted on a circuit board. One of the DCNs comprises an impedance Z.sub.1 connected across pins 10 and 12 of U1. A second DCN comprises a delta network made up of impedances Z.sub.2, Z.sub.3 and Z.sub.4 connected between U1 and U2 and uses two pins of each IC. The third DCN comprises an impedance Z.sub.5 connected between one pin on U2 and one pin of U3. Analog bus 28 in each IC is connected to a current source I.sub.s, and analog bus 30 in each IC is connected to a voltmeter V.sub.m through the bus pins of each IC.
The metrology of the aforementioned patent application can be used to measure the values of Z.sub.1, Z.sub.2, Z.sub.3, Z.sub.4, and Z.sub.5. and can be explained by considering an impedance Z connected between any two test cell as shown in FIG. 4(a). The metrology comprises the following steps.
Step 1: Configure the test cells as shown in FIG. 4(b) by closing S.sub.1 and S.sub.2 in Cell 1, G in Cell 2 and opening all other switches. V.sub.m will show voltage V.sub.1 at Pin 1. PA0 Step 2: Configure the cells as shown in FIG. 4(c) by closing S.sub.1 in Cell 1, S.sub.2 and G in Cell 2 and opening all other switches. V.sub.m will show voltage V.sub.2 at pin 2.
Step 3: Compute Z as ##EQU1##
The testing approach used in the above procedure is to pass a fixed current through Z and measure voltages at the Pins 1 and 2 between which the impedance is connected. The value of Z can then be computed using Ohm's law. The voltmeter V.sub.m has very high impedance compared to the ON-resistance R.sub.s2 of switch S.sub.2 in Cell 1. Therefore, in Step 1, R.sub.s2 can be ignored in the computations to obtain a voltage at Pin 1 of V.sub.1 =(Z+R.sub.G)I.sub.S, where R.sub.G is the ON-resistance of switch G in Cell 2. In Step 2, the ON-resistance of switch S.sub.2 in Cell 2 is ignored in the computations to obtain a voltage at Pin 2 of V.sub.2 =R.sub.G I.sub.S. The effect of R.sub.G is canceled when Z is computed in Step 3. This procedure requires two configurations of the cells, controlled by a JTAG/IEEE 1149.1 TAP controller.
The above testing procedure can be used to verify either Z.sub.1 or Z.sub.5 of FIG. 3. The testing of the delta network of FIG. 3 can be similarly accomplished. A total of six configurations of the four cells at the four pins are needed to test the delta network. In the method just described, the ON-resistance R.sub.S1 of switch S.sub.1 in Cell 1 does not affect the computations as the switch is not in the path of the voltmeter. This is generally true for the metrology of the aforementioned patent application, where a separate bus is used for connecting the voltmeter to the pin under consideration.
It would be advantageous if a single bus could be used to connect both the current source and the voltmeter to the DCN. Such a structure would result in lower overhead in pins and board area. One possible single bus approach is shown in FIG. 5. In order to pass a constant current from the source I.sub.s through DCN 50 over bus 52, it is necessary to close switch S. However, the voltmeter then measures the voltage at the bus pin 54 and not at analog test pin 56 as desired. Thus, the ON-resistance of Switch S represented at 58 would affect the voltage measured by the voltmeter V.sub.m.